Method for plating using nested plating buses and semiconductor device having the same

ABSTRACT

Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

FIELD OF THE INVENTION

The present invention relates to plating and plated devices in general,and more specifically to plating using nested plating buses andsemiconductor devices having such nested plating buses.

BACKGROUND OF THE INVENTION

Due to the constant push for smaller and smaller products, it has becomecommon for integrated circuits (ICs) once contained on two or moreindividual semiconductor die or chips to be combined into a single,larger IC device. For example, traditional microprocessor circuits arebeing combined on a single chip with digital signal process circuits.These combined ICs have the advantage of better reliability due to fewertotal external connections, but have higher input/output (I/O) countsthan many of the individual ICs. Often, these combined devices have I/Osin the 200+ range. Additionally, new ICs are being designed "from theground up" with many advanced features which also result in 200+ I/Os.Thus, high I/O counts are becoming more and more commonplace.

Over Molded Pad Array Carrier or OMPAC is one successful method forcontaining relatively large I/O count into a small footprint at lowcost. The OMPAC package (a type of ball grid array or BGA package)consists of a printed circuit board (PCB) or other insulating materialsubstrate having a plurality of conductive traces on both the top andbottom surfaces, vias connecting the top traces to the bottom traces,and solder pads at ends of the bottom traces. The traces, vias, andpads, are typically formed of copper and are subsequently plated withnickel and gold. A semiconductor die is attached to the top of thesubstrate, and wires are used to electrically couple the die to the topset of traces. An organic encapsulation is applied over the die, wiresand portions of the top of the substrate. A mass of solder in the formof spheres, paste, or plating is then applied to the solder pads on thebottom of the package. Since OMPAC packages have an array of solder padscovering most of the package bottom, the package is typically muchsmaller than corresponding peripherally leaded packages. An array takesadvantage of the entire area of the package, whereas peripherally leadedpackages can only take advantage of the outer perimeter of the package.

Due to the basic nature of the package components, OMPAC is considered alow cost package. The most expensive individual cost component is thesubstrate. The cost of a single layer, double sided substrate issignificantly lower than that of a multilayer substrate and is thereforepreferred for OMPAC applications. One of the limitations of single layersubstrates is the restriction in routing electrical connections from thevias to an external plating bus formed at the periphery of the package.Electrical connections to the plating bus are required for electrolyticplating of nickel and gold onto those portions of the copper laminatewhich will be used for subsequent electrical bonding (i.e. die bonding,wire bonding, and solder ball reflow) or for electrical probing andtesting. The nickel and gold plating layers protect the copper fromoxidation, resulting in a surface which is easier to bond and probe. Inorder to accomplish electrolytic plating, all conductive parts which areto be plated are electrically short-circuited so that necessary currentapplied during the electrolytic process easily passes through allmembers to be plated. This is typically accomplished by routing allmembers to an external plating bus. The bus must eventually be removedto create electrical isolation between the various conductive features.

To achieve a higher I/O count without increasing package size andwithout moving to a multiple layer substrate, the routing density (i.e.number of traces per unit area) on the outer surfaces must be increased.The routing density of a substrate used in OMPAC packages is dictated bythe size of the via holes, the size of the annular rings surroundingeach via hole, the solder pad diameter, the minimum copper trace widthand the minimum gap between copper traces. Depending on the capabilitiesof the substrate manufacturer and on the I/O count of the package, theexternal plating connections also often directly limit the number ofdiscrete I/O connections possible for single layer substrate packages.In other words, the need to connect all traces to an external,peripheral plating bus often restricts the routing density for a givensize substrate.

In the case of a typical OMPAC substrate, (assuming 1.5 mm solder padpitch, 0.25 mm via diameter, 0.50 mm annular via ring diameter, 0.89 mmsolder pad diameter, 0.1 mm copper trace width and 0.1 mm gap betweencopper traces), it is possible to have up to 3 traces between vias onthe top surface of the package, and to have up to 2 traces betweensolder pads on the bottom surface. These traces can be used to eitherroute from wire bond fingers to vias (where wire bond fingers are padsat the ends of top surface traces which surround the die and whichreceive the bonding wires), or from vias to the external plating bus.These figures put a lower limit on the size of a particular substratefor a given number of I/Os. In order to achieve additional routing, andthus a higher I/O count, with the current single layer OMPAC substrates,the via and solder pad pitches would have to be increased to allow moretraces to fit between pads and vias, or the via and solder pad diameterswould have to be decreased. Increasing the solder pad and via pitchesundesirably increases the size of the substrate and size of the finalpackage, whereas decreasing solder pad and via diameters wouldundesirably increase the cost to manufacture the substrate and reducethe solder joint strength due to the smaller solder pads. Accordingly,it would be desirable to eliminate the need to route traces to externalplating buses. This would reduce the number of traces that need to berouted between vias and between solder pads, thereby keeping substratesize to a minimum while increasing routing density.

One known solution to the routing problem imposed by the need to routetraces to an external plating bus is the use of so-called "electroless"plating processes. External plating connections would not be required ifthe substrates were nickel and gold plated using electroless platingtechniques since electroless plating does not require all conductiveelements to be short-circuited together. However, electroless plating isinherently thinner and more porous than electrolytic plating which makesit marginal at preventing oxidation of the underlying copper. This inturn makes it more difficult to achieve good, reliable bonding onto theplated surfaces. Consequently, the use of electroless gold plating islimited to special cases where the time and temperature exposures areshort and low enough that the resulting oxidation does not impede thecreation of reliable bonds.

Therefore, an alternative to the existing external peripheral platingbus used in OMPAC semiconductor devices, and similar devices havingwired substrates, would be desirable. Moreover, such an alternativeshould improve the existing plating process by allowing more traces andvias to be formed in a given area of the substrate than presentlypossible.

SUMMARY OF THE INVENTION

In accordance with one form of the invention, a plating method is usedto plate a plurality of radially arranged conductive members. Eachconductive member has an inner end and an outer end. The plurality ofconductive members is divided into a first group of conductive membersand a second group of conductive members. Each outer end of conductivemembers in the first group is connected to an outer plating bus. Eachinner end of the conductive members of the second group is connected toa nested plating bus inside the outer plating bus, while each outer endof the conductive members of the second group is unconnected to theouter plating bus. The conductive members of both the first and secondgroup are then plated. In another form of the present invention, asemiconductor device includes features of a substrate plated by such amethod.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view of a portion of a substrate used for plating, andfor making a semiconductor device, in accordance with the presentinvention.

FIG. 2 is an exploded view of a portion of the substrate illustrated inFIG. 1.

FIG. 3 is a cross-sectional view of a semiconductor device utilizing asubstrate such as that illustrated in FIG. 1, also in accordance withthe present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

The present invention increases the maximum possible I/O count for agiven substrate size by allowing a nested plating bus to complement theexisting external plating bus. In addition, the use of the nestedplating bus reduces or eliminates the need for bottom side electricalrouting which should improve package reliability and electricalperformance by increasing the distance between discrete conductivetraces, vias and solder pads on the bottom side of the substrate.

These and other features, and advantages, of the present invention willbe more clearly understood from the following detailed description takenin conjunction with the accompanying drawings. It is important to pointout that the illustrations may not necessarily be drawn to scale, andthat there may be other embodiments of the present invention which arenot specifically illustrated. Also, like reference numerals may be usedthroughout the various views, indicating identical, corresponding, orsimilar elements.

FIG. 1 is a top view of a portion of a PCB or other insulating materialsubstrate 10 which is plated by a method in accordance with the presentinvention. The electrical usefulness of the substrate for an electronicapplication is created by various conductive elements. These include aplurality of plated through holes or vias 12, a plurality of conductivetraces 14, an external plating bus 16, a nested plating bus 18, and aplurality of bonding fingers 20. In a preferred embodiment of thepresent invention, each of these conductive members is formed oflaminated or deposited copper. Conductive traces 14 can be located onany signal routing layer (top or bottom surfaces of single layer doublesided substrates, or internal layers of multilayer substrates).Conductive traces 14 are used to route from bonding fingers 20 to vias12 which are in turn connected to solder pads (not shown) on the bottomof substrate 10. The portions of the traces connecting bonding fingers20 to vias 12 are electrically functional in a finished semiconductordevice in that these portions are used to transmit signals during deviceoperation. For electrolytic plating purposes, the conductive traces 14are routed to either the nested plating bus 18 which lies within thefinished package outline 24, or to the external plating bus 16 whichlies outside the finished package outline 24. Finished package outline24 represents where substrate 10 will be excised to form a completedsemiconductor device. The portions of the traces used to route from viasto a plating bus are necessary only for plating purposes, not forfunctional purposes during semiconductor device operation. Asillustrated, nested plating bus 18 also lies within a die receiving area22, which represents the area of substrate 10 onto which a semiconductordie (not shown in FIG. 1) will eventually be mounted. However, it isimportant to note that the present invention does not require that thenested plating bus be within the die receiving area. Benefits of thepresent invention are reaped as long as the nested plating bus lieswithin the external finished package outline.

FIG. 2 is an exploded view of highlighted region 28 of FIG. 1. As shown,conductive traces 14 are connected to vias 12 both above and below therow of bonding fingers 20, and are then routed to either the nestedplating bus 18 or to the external plating 16. Traces connected to viasbelow the row of bonding fingers are a first group of traces, and arealso connected to external plating bus 16. Traces connected to viasabove the row of bonding fingers are a second group of traces, and arealso connected to nested plating bus 18. In the example shown, it ispossible to route conductive traces 14 to eight rows of vias 12, fourrows on either side of the row of bonding fingers 20. As illustrated inFIG. 2, all of the routing is on the top side of the substrate whichmaximizes the electrical isolation on the bottom side of the substrate.In prior art substrates, routing is often needed on both the top andbottom sides of the substrate. However, manufacturers would like toeliminate any unnecessary surface routing for several reasons. Onereason is that extraneous routing may create noise during deviceoperation. Another reason is that the more routing there is on thesurface, the more likely unwanted short-circuiting will occur betweenadjacent conductive members.

Current single layer OMPAC substrates only utilize an external platingbus, such as external plating bus 16. With use of only an externalplating bus, and assuming the feature dimensions listed in thebackground, conductive traces can be routed to only a maximum of sixrows of vias. Moreover, to achieve this maximum 6 rows of vias,substrate designs require two conductive traces between vias on thebottom side of the substrate, in addition to three conductive tracesbetween vias on the top side of the substrate. The use of both top andbottom side traces in current substrates is undesirable both from amanufacturing/reliability point of view, and from a device operationalperformance point of view, as discussed above. The present inventionpermits eight rows of vias without any bottom side traces. Thus, moreI/Os can be achieved in a single layer substrate using a plating methodin accordance with the present invention, then if using a traditionalplating method for a single layer substrate. Moreover, the higher I/Ocount possible with the present invention can be achieved by routing ononly one surface of the substrate, whereas multilayer routing would benecessary to achieve comparable I/O counts on existing substrates andwith existing plating techniques. It is important to note, however, thatthe present invention is not limited to plating substrates having onlyone-sided routing. Benefits of the present invention can also beobtained in substrates having multiple layers of routing, both externaland internal.

FIG. 3 is a cross-sectional view of an OMPAC semiconductor device 30 inaccordance with the present invention. Device 30 includes a portion ofsubstrate 10, namely that portion denoted by finished package outline 24of FIG. 1. Also in device 30 is a semiconductor die 34 attached to thesubstrate 10 by means of an adhesive die attach 36. Bonding wires 38 areused to connect the semiconductor die 34 to plated conductive traces 14,or more specifically to bonding fingers 20 at the ends of the conductivetraces (although in FIG. 3, the bonding fingers and traces areindistinguishable). A resin package body 40 is then molded or dispensedover the semiconductor die 34, the bonding wires 38, and over mostportions of the top side of substrate 10 to provide environmentalprotection. A mass of solder in the form of spheres, paste or plating 44is then applied to a plurality of solder pads 42 formed on the bottomside of substrate 10. The pads are electrically coupled to thesemiconductor die through vias 12, bonding wires 38 and conductivetraces 14. Many of the manufacturing operations thus far described canbe performed while substrate 10 is in a strip or sheet form having manydie or device sites. At some stage in manufacturing, device 30 isremoved from the surrounding substrate material and forms the outsidedimension (the finished package outline) 24 of the individualsemiconductor device 30. In one embodiment of the present invention,device 30 is excised after molding package body 40 and after theapplication of solder 44 to solder pads 42, being practically the lastvalue-added manufacturing step. In another embodiment, excision occursafter molding but before solder 44 is applied.

As illustrated in FIG. 3, substrate 10 has an etched/milled area 32which is where a nested plating bus, and perhaps inner portions ofconductive traces 14, have been removed from substrate 10 so that theconductive traces are no longer electrically short-circuited together.Area 32, in preferred embodiments, is formed using known etching ormilling techniques. Instead, the nested plating bus may be severed bymeans of punching or other material removal processes. Although a solidarea has been removed from substrate 10 as illustrated in FIG. 3, it isalso possible to sever the nested plating bus by removing a smallerportion of the substrate, for instance by milling a shape or outlinewhich conforms to the shape of the bus (e.g. a rectangular groove). Itis also appropriate to note that the shape of a nested plating bus isnot important to practicing the invention.

As illustrated in FIG. 3, trace 14 in the left half of device 30 beginsat bonding finger 20 and terminates at the edge of removed area 32.Thus, the right end of this trace was previously connected to a nestedplating bus in accordance with the present invention. The trace 14 inthe right half of device 30 likewise begins at bonding finger 20, butextends away from area 32 to the finished package outline 24 ofsubstrate 10. Thus, the right end of this trace was previously connectedto an external plating bus. As also illustrated in FIG. 3, each trace 14is divided into two portions, a functional portion 46 and a platingportion 48. The functional portion 46 of each trace is that portion ofthe trace which electrically couples die 34 to an external I/Oconnection, such as solder ball 44. The plating portion 48 of each traceis that portion of the trace which routes the trace to a plating bus,either external or nested, but is otherwise not necessary for deviceoperation. Another term for plating portions 48 known in the art indevices having only external plating buses (e.g. like in the right handportion of device 30) is a plating stub.

The foregoing description and illustrations contained herein demonstratemany of the advantages associated with the present invention. Inparticular, it has been revealed that use of a nested plating busincreases the maximum possible I/O count for a given substrate.Moreover, the use of a nested plating bus reduces the requirement forbottom side electrical routing which should improve package reliabilityand electrical performance by increasing the distance between conductivetraces and metal features. Another advantage is that depending on thespecific substrate configuration, use of a nested plating bus can reducethe length of the plating connections which will reduce electricalparasitics and thus enhance the performance of the semiconductor device.

Thus it is apparent that there has been provided, in accordance with theinvention, a method for plating using nested plating buses and asemiconductor device having the same, that fully meets the need andadvantages set forth previously. Although the invention has beendescribed and illustrated with reference to specific embodimentsthereof, it is not intended that the invention be limited to theseillustrative embodiments. Those skilled in the art will recognize thatmodifications and variations can be made without departing from thespirit of the invention. For example, multilayer substrate designs arenot shown but will be subject to the limitations and advantagesdiscussed for single layer substrates. In addition, the invention is notlimited to any particular shape for a nested plating bus. Furthermore, asubstrate used in accordance with the present invention may utilizefilled vias as opposed to plated through holes. Furthermore, while adescription of the present invention included the elimination of bottomside routing in accordance with one embodiment, the benefits of thepresent invention can likewise be achieved in substrates which have bothtop and bottom side routing, either top or bottom side routing alone, orexternal surface routing in conjunction with internal surface routing.Moreover, the present invention may be practiced wherein a nestedplating bus is on one surface of a substrate while the external platingbus is on the opposing surface. In addition, the present invention isnot limited to applications of OMPAC semiconductor devices or ball gridarrays, but instead can be used in any device or process which is to beplated. Therefore, it is intended that this invention encompass all suchvariations and modifications as fall within the scope of the appendedclaims.

What is claimed is:
 1. A method for plating a plurality of radiallyarranged conductive members, wherein each conductive member has an innerend and an outer end and wherein the plurality of conductive members isdivided into a first group of conductive members and a second group ofconductive members, comprising the steps of:connecting the outer end ofeach member of the first group to an outer plating bus; connecting theinner end of each member of the second group to a nested plating busthat is inside the outer plating bus, without connecting the outer endof each member of the second group to the outer plating bus; and platingthe plurality of conductive members.
 2. The method of claim 1 whereinthe plurality of conductive members comprise a plurality of conductivetraces on a surface of a printed wiring substrate.
 3. The method ofclaim 2 wherein the printed wiring substrate has a plurality of bondingfingers for wire bonding to a semiconductor die, and wherein the innerend of each member of the first group is connected to a correspondingbonding finger, and the outer end of each member of the second group isconnected to a different corresponding bonding finger than thecorresponding bonding finger of each member of the first group.
 4. Themethod of claim 3 wherein the plurality of bonding fingers divides theplurality of conductive members into the first and the second groups ofconductive members.
 5. A method for plating a wiring substratecomprising the steps of:providing an insulating substrate materialhaving .[.a surface,.]. a package receiving area, and a die receivingarea within the package receiving area; forming an outer plating bus on.[.the surface of.]. the substrate .[.which.]., .Iadd.wherein the outerplating bus .Iaddend.substantially surrounds the package receiving area;forming a nested plating bus on .[.the surface of.]. the substrate andwithin the outer plating bus; forming a first plurality of conductivetraces on .[.the surface of.]. the substrate and within the packagereceiving area, the first plurality of traces being connected to theouter plating bus; forming a second plurality of conductive traces on.[.the surface of.]. the substrate and within the package receivingarea, the second plurality of traces being connected to the outerplating bus; and plating the first and the second pluralities ofconductive traces.
 6. The method of claim 5 wherein the first and secondpluralities of conductive traces are physically separated from oneanother by a plurality of conductive bonding fingers formed on the.[.the surface of.]. the substrate and substantially surrounding the diereceiving area.
 7. The method of claim 5 wherein the steps of formingthe outer plating bus, the nested plating bus, the first plurality ofconductive traces, and the second plurality of conductive traces areaccomplished simultaneously.
 8. The method of claim 5 wherein the outerplating bus and the nested plating bus are both substantiallyrectangular rings.
 9. The method of claim 5 further comprising the stepof removing the nested plating bus from within the package receivingarea to form a plurality of plating stubs.
 10. The method of claim 9wherein the step of removing the nested plating bus comprises chemicallyetching the nested plating bus.
 11. The method of claim 9 wherein thestep of removing the nested plating bus comprises mechanically removingthe nested plating bus.
 12. The method of claim 5 wherein the nestedplating bus is formed within the die receiving area of the substrate.13. A method for making a semiconductor device comprising the stepsof:providing a wiring substrate made in accordance with a methodcomprising the steps of:providing an insulating substrate materialhaving .[.a surface,.]. a package receiving area, and a die receivingarea within the package receiving area; forming an outer plating bus on.[.the surface of.]. the substrate which substantially surrounds thepackage receiving area; forming a nested plating bus on .[.the surfaceof.]. the substrate and within the outer plating bus; forming a firstplurality of conductive traces on .[.the surface of.]. the substrate andwithin the package receiving area, the first plurality of traces beingconnected to the outer plating bus; forming a second plurality ofconductive traces on .[.the surface of.]. the substrate and within thepackage receiving area, the second plurality of traces being connectedto the nested plating bus without being connected to the outer platingbus; plating the first and the second pluralities of conductive traces;and removing the nested plating bus from the .[.surface of the.].substrate, leaving a plurality of plating stubs on the .[.surface.]..Iadd.substrate;.Iaddend. providing a semiconductor die; positioning thedie within the die receiving area; electrically coupling the die to thefirst and the second pluralities of conductive traces; and encapsulatingthe die in a protective body.
 14. The method of claim 13 wherein thestep of positioning the die comprises positioning the die over theplurality of plating stubs.
 15. The method of claim 13 furthercomprising the step of excising the package receiving area of thesubstrate from remaining portions of the substrate.
 16. A semiconductordevice comprising:a printed wiring substrate having a periphery, asurface, a die receiving area on the surface, a plurality of conductivebonding fingers formed on the surface and surrounding the die receivingarea, a first plurality of conductive vias extending through thesubstrate and positioned within the plurality of conductive bondingfingers, a second plurality of conductive vias extending through thesubstrate and positioned without the plurality of conductive bondingfingers, wherein each via of the first and the second pluralities ofvias has two associated trace portions on the .[.surface.]..Iadd.substrate, .Iaddend.a bonding trace portion and a plating traceportion, wherein the bonding trace portion of each via of the first andthe second pluralities of vias is routed to a corresponding bondingfinger, and wherein the plating trace portion of each via in the secondplurality of vias is routed outward to the periphery of the substratewhile the plating trace portion of each via in the first plurality ofvias is routed inward toward a center of the substrate; a semiconductordie positioned within the die receiving area; means for electricallycoupling the die to the plurality of bonding fingers on the substrate;and a protective body encapsulating the semiconductor.
 17. Thesemiconductor device of claim 16 further comprising a recessed portionin .[.the surface of.]. the substrate within the plurality of bondingfingers, and wherein the plating trace portion of each via in the secondplurality of vias terminates at the recessed portion.
 18. Thesemiconductor device of claim 16 wherein the printed wiring substrate isselected from a group consisting of: a printed circuit board and aceramic substrate.
 19. A semiconductor device comprising:a printedwiring substrate having a periphery, .[.a surface,.]. a die receivingarea on the .[.surface.]. .Iadd.substrate, .Iaddend.a first and a secondplurality of conductive vias extending through the substrate, and aplating trace connected to each via of the first and the secondpluralities of vias, wherein the plating traces associated with thefirst plurality of vias exist on the .[.surface.]. .Iadd.substrate.Iaddend.and terminate at the periphery of the substrate and the platingtraces associated with the second plurality of vias exist on the.[.surface.]. .Iadd.substrate .Iaddend.and terminate near the diereceiving area; a semiconductor die positioned within the die receivingarea; means for electrically coupling the semiconductor die to the firstand the second pluralities of vias; and means for providingenvironmental protection to the semiconductor die.
 20. The semiconductordevice of claim 19 wherein the printed wiring substrate is selected froma group consisting of: a printed circuit board and a ceramic substrate.21. The semiconductor device of claim 19 further comprising a functionaltrace associated with each via of the first and the second pluralitiesof vias for carrying signals to the semiconductor die.